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  ModelSim Designer °ü·ÃÀÚ·á
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Design Creator HDL Designer HDL Author HDL Detective
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FPGA Advantage ¼Ò°³ °ü·ÃÀÚ·á
 
 
 

HDL Author

HDL Author¢âÀº º¹ÀâÇÑ hierarchical design°ü¸® ¹× HDL design¼³°è¸¦ º¸´Ù ½±°Ô ÇÒ ¼ö Àִ ȯ°æÀ» Á¦°ø ÇÕ´Ï´Ù.

  • Advanced HDL design development and analysis environment
  • HDL entry and code generation via a variety of graphical, tabular and textual editors
  • Works seamlessly with industry-standard simulation and synthesis tools


Benefits


  • Facilitates management of complex, multi-discipline ASIC/FPGA system-level RTL design projectsEnables an HDL design engineer to easily collaborate on design development with other teams of engineers
  • Satisfies all design creation needs via textual, tabular and graphical design entry editors
  • Designers can use a favorite HDL simulator and synthesis engine, creating an easier, more productive HDL design process
  • Integrates other design tools easily with TCL, to run from within the HDL Author¢â environment