 HDL Designer
HDL Designer Series State Diagram, Flow Chart, Truth Table, Block Diagramκ
ռ Verilog VHDL ڵ带 ڵ ϴ HDL Graphical Design ȯԴϴ.
Import HDL Block-based Design Methodology Ǵ ϱ
VHDL IP(Intellectual Property) , Verilog IP, HDL Text Graphical Design ȯŴν
꼺 ų ̷ ɵ Design management ȿ شȭ ݴϴ.
Features
- Enables
scalable RTL design, spanning FPGAs to multimillion gate ASICs
- Creates
and manages complex Verilog, VHDL, and mixed-language ASIC and FPGA
designs
- Provides a
variety of text, tabular and graphical design creation methods to suit
different designers and design tasks
- Automatically
produces graphical and HTML documentation for design reviews, archival and
reuse
- Delivers advanced
static analysis up front in the design process, with graphical simulation
debug (with DesignAnalyst option)
Benefits
- Facilitates development across distributed design teams through data
management and version controlEnables practical design reuse through rapid understanding and easy
deployment of IP
- Satisfies all design creation needs via textual, tabular and graphical
development with other teams of engineers
- Designers can use a favorite HDL simulator and synthesis engine, creating an
easier, more productive HDL design process
- Integrates other design tools easily with TCL, to run from within the HDL
Author environment
|
|
