 HDL Designer
HDL Designer Series는 State Diagram, Flow Chart, Truth Table, Block Diagram으로부터
합성 가능한 Verilog 와 VHDL 코드를 자동으로 생성하는 HDL Graphical Design 환경입니다.
또한 Import HDL는 Block-based Design Methodology에서 증가되는 디자인의 재사용을 지원하기 위해
VHDL IP(Intellectual Property) , Verilog IP, HDL Text를 Graphical Design으로 변환시킴으로써
생산성을 비약적으로 향상시킬 수 있으며 이러한 기능들은 Design management의 효율성을 극대화 시켜줍니다.
Features
- Enables
scalable RTL design, spanning FPGAs to multimillion gate ASICs
- Creates
and manages complex Verilog, VHDL, and mixed-language ASIC and FPGA
designs
- Provides a
variety of text, tabular and graphical design creation methods to suit
different designers and design tasks
- Automatically
produces graphical and HTML documentation for design reviews, archival and
reuse
- Delivers advanced
static analysis up front in the design process, with graphical simulation
debug (with DesignAnalyst™ option)
Benefits
- Facilitates development across distributed design teams through data
management and version controlEnables practical design reuse through rapid understanding and easy
deployment of IP
- Satisfies all design creation needs via textual, tabular and graphical
development with other teams of engineers
- Designers can use a favorite HDL simulator and synthesis engine, creating an
easier, more productive HDL design process
- Integrates other design tools easily with TCL, to run from within the HDL
Author™ environment
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