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Leonardo Spectrum
Leonardo SpectrumÀº ¾÷°è ÃÖÃÊÀÇ Platform-Independent FPGA/ASIC Synthesis ȯ°æÀ¸·Î¼ Á¾·¡ÀÇ Synthesis ToolÀÌ °í·ÁÇÏÁö ¸øÇß´ø ÅëÇÕÀûÀΠȯ°æÀ» Á¦°øÇÕ´Ï´Ù. Áï, ´Ü¼øÈ÷ RTL ±â¼ú¿¡¼ ½ÃÀÛÇϰųª ¡°Place and Route¡± tool¿¡ Synthesis °á°ú¸¦ Àü´ÞÇÏ´Â °ÍÀ¸·Î ³¡³»Áö ¾Ê½À´Ï´Ù. Leonardo SpectrumÀº ¾÷°è¿¡¼ °¡Àå °·ÂÇÑ Design Creation, Simulation, Synthesis, ±×¸®°í Implementation Technology¸¦ °£´ÜÇϰí ÀÌÀ½»õ ¾ø´Â °úÁ¤À¸·Î ÅëÇÕÇÏ¿© FPGA³ª ASICÀ» ¼³°èÇÒ ¶§ µ¿ÀÏÇÑ ¼³°èȯ°æÀ» Á¦°øÇÕ´Ï´Ù.
- Push-button ease-of-use for designing PLDs, FPGAs and ASICs, in VHDL or
Verilog
- HDLInventor¢â creates optimized HDL code fast and facilitates company-wide
sharing of IP
- P&R Integrator¢â simplifies place-and-route and delivers improved results
- Opens access to advanced synthesis controls within PowerTabs
- Proprietary ease-of-use features such as FlowTabs¢â and QuickSetup ease
first-time FPGA synthesis
- Offers true hierarchical support for incremental synthesis
- Schematic Fragment Generator gives quick insight into a design¡¯s
behavior
Benefits
- One tool, one easy learning curve, one set of scripts -- for CPLDs, FPGAs,
or ASICsUsers can mix VHDL, Verilog and EDIF, enabling design reuse and
instantiation of IP
- Provides high QoR with the speed and features needed for large designs
- Built-in partitioning speeds ASIC prototyping and verification process
- True hierarchical support makes it easy to group and ungroup design
elements, which can then be targeted for single or multiple chips
- Offers users language neutrality, and both platform- and target device
independence
- Exclusive five-way cross-probing among multiple design views in
LeonardoInsight accelerates synthesis analysis
- Schematic Fragment Generator optimizes area and performance
tradeoffs


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