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 Precision Physical
- Precision Physical Synthesis ڵȭ Physical Synthesis Flow Interactive Fix-up ȯ ߰ν Precision RTL Synthesis Ȯ ǰԴϴ.
ǰ ٸ ȸ ռ ռ Ÿ̹(timing) ߴµ ǰ ֽϴ. Physical Synthesis ɰ Ͽ physical (Place & Route data) ռ ˰(synthesis algorithm) νŰ , Precision RTL Synthesis ռϰ (vendor) Place & Route Ŀ ̿ ϰ ˴ϴ.
Physical Synthesis ˰ re-timing, replication, re-synthesis and placement optimization 3 ȭ ؼ ˴ϴ.
Features
- Integrated RTL and physical FPGA synthesis solution, built on a single data
model, simultaneously optimizes gate and interconnect delay
- Fully automated, or optional interactive optimization for advanced users
- Comprehensive physical to RTL cross-probing capabilities
- Powerful timing engine for advanced and detailed timing analysis
- Conforms to the standard Synopsys® Design Constraints (SDC) language for
constraint creation
- Powerful, ASIC-strength synthesis algorithms for retiming, replication,
re-placement and re-synthesis
- Integrates PreciseView, an automated and interactive physical editing
environment
Benefits
- Takes advantage of the FPGA vendors initial place-and-route results to
target physical optimizations for quick timing convergenceEnables users to cross-probe from the detailed timing report to the RTL
source code, RTL schematic or the physical layout
- Timing engine performs incremental analysis, such that changes to the design
or constraints only cause small portions of the design to be recalculated
- Since many tools accept SDC, constraints typically will be readily available
for a design
- Easily pinpoints missing timing constraints and thus avoids timing problems
in the lab
- Displays clock domain crossings, so designers can ensure that none of these
paths are really critical
- Displays clock propagation paths, which helps debug clock-skew issues
- Reports timing paths against constraints, or as delay paths for complete
debugging flexibility
- Reduces design iteration times by achieving performance and design goals
quickly and predictably
- Efficient synthesis environment deterministically reduces design time by
weeks or months and significantly improves performance
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