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 Precision Physical
- Precision Physical Synthesis는 자동화된 Physical Synthesis Flow와 Interactive Fix-up 환경을 추가함으로써 Precision RTL Synthesis의 기능을 확장한 제품입니다.
또 이 제품은 다른 회사의 합성 툴에 의해 합성된 디자인의 타이밍(timing)을 맞추는데도 사용되고 있습니다. Physical Synthesis는 더 좋은 성능과 결과를 얻기 위하여 physical 정보(Place & Route data)를 합성 알고리즘(synthesis algorithm)에 결부시키는 과정으로, Precision RTL Synthesis로 디자인을 합성하고 벤더(vendor) 툴로 Place & Route를 수행한 후에 이와 같은 성능을 발휘하게 됩니다.
Physical Synthesis 알고리즘은 re-timing, replication, re-synthesis and placement optimization과 같은 3가지 최적화 기술에 의해서 수행됩니다.
Features
- Integrated RTL and physical FPGA synthesis solution, built on a single data
model, simultaneously optimizes gate and interconnect delay
- Fully automated, or optional interactive optimization for advanced users
- Comprehensive physical to RTL cross-probing capabilities
- Powerful timing engine for advanced and detailed timing analysis
- Conforms to the standard Synopsys® Design Constraints (SDC) language for
constraint creation
- Powerful, ASIC-strength synthesis algorithms for retiming, replication,
re-placement and re-synthesis
- Integrates PreciseView, an automated and interactive physical editing
environment
Benefits
- Takes advantage of the FPGA vendor’s initial place-and-route results to
target physical optimizations for quick timing convergenceEnables users to cross-probe from the detailed timing report to the RTL
source code, RTL schematic or the physical layout
- Timing engine performs incremental analysis, such that changes to the design
or constraints only cause small portions of the design to be recalculated
- Since many tools accept SDC, constraints typically will be readily available
for a design
- Easily pinpoints missing timing constraints and thus avoids timing problems
in the lab
- Displays clock domain crossings, so designers can ensure that none of these
paths are really critical
- Displays clock propagation paths, which helps debug clock-skew issues
- Reports timing paths against constraints, or as delay paths for complete
debugging flexibility
- Reduces design iteration times by achieving performance and design goals
quickly and predictably
- Efficient synthesis environment deterministically reduces design time by
weeks or months and significantly improves performance
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