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 Precision RTL
- Precision RTL Synthesis ϴ programmable logic devices(CPLDs and FPGAs) 鸸 Ʈ FPSoC(Field Programmable System-on-Chip) devices شȭ ִ ռ ÷(Synthesis Platform)Դϴ.
- Precision RTL Synthesis RTL logic synthesis, VHDL/Verilog design capture, constraint-based optimization, ֽ timing analysis, schematic viewing, ȭ place-and-route ȯ ϴ Ʋ(Tool)ν, PC platforms(Windows 2000/NT/XP, Linux Red Hat), Unix Sun HP Platforms ˴ϴ.
Features
- High-performance, easy-to-use, vendor-independent RTL synthesis solution
- Offers built-in schematic viewing of RTL and FPGA designs
- Retiming algorithm moves registers across logic to improve performance
- Interactive PreciseTime feature quickly performs what-if timing analysis
- Design Bar guides users step-by-step through synthesis, analysis, and
place-and-route
- Constraint analysis feature identifies missing constraints
Benefits
- Improves designer efficiency through an intuitive user interfaceExcellent quality of results using advanced optimization techniques
- Advanced, incremental debug and analysis environment identifies and fixes
problems early in the design process
- Language neutrality supports any combination of VHDL, Verilog, and EDIF
format
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