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Auspy
Automatic Multi-FPGA Partitioning Solution
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Autodesk
Plastic Injection Molding Solution
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ChipVision
High-Level Synthesis solution for Power Efficient RTL Generation from ESL |
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ClioSoft
Design Data Management & Version Control
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Concept Engineering
Netlist Visualization & Analyzer for Gate-level netlist & SPICE netlist |
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INCENTIA
Full-Chip Gate-level Static Timing Analyzer |
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Legend Design
Best-in-class characterization tool for memory, standard cell and I/O cell.
High-Speed & High-accuracy Circuit Simulator |
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Mentor Graphics
ModelSim, Questa, Calibre, ADvanceMS, ADiT, 0-in
Catapult-C, Precision, PADS, Board Station, Expedition HyperLynx, Veloce, etc.
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Orora Design Technologies
Parasitic-included Optimization & Behavioral Model Generation from SPICE to Verilog/VHDL AMS/Matlab
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Temento Systems
On-Chip FPGA verification Tool
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TOOL CORPORATION
Next Generation fastest Layout Viewer & Fracturing solution |
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