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ChipVision
Power Estimation & Analysis Solution for System Level |
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ClioSoft
Design Data Management & Version Control
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Concept Engineering
Netlist Viewer & Analyzer for gate-level netlist & SPICE model |
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INCENTIA
- Fastest STA & constraint Manager
- Logic Synthesis & Physical Synthesis
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Legend Design
Memory Characterization, SpiceCut Library, Characterization
Oriented Circuit Simulator with RC reduction |
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Mentor Graphics
ModelSim, Questa, PADS, HyperLynx, I/O Designer
Dx Designer, RSI, VeSys
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Orora Design Technologies
- Automated Circuit Analysis & Visualization
- Synthesis & Optimization |
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TOOL CORPORATION
Next Generation
Standard Layout
Viewer
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TransEDA
Functional Verification Solution - Code Coverage, Linter
and Verification IP,assertion |
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Pro Design
High-Speed Prototyping Platforms
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Auspy
Automatic Multiple-FPGA Partiting Solution
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