|
|
|
| |
|
 |
Auspy
Automatic Multi-FPGA Partitioning Solution
|
| |
|
 |
Autodesk
Plastic Injection Molding Solution
|
| |
|
 |
ChipVision
High-Level Synthesis solution for Power Efficient RTL Generation from ESL |
| |
|
 |
ClioSoft
Design Data Management & Version Control
|
| |
|
 |
Concept Engineering
Netlist Visualization & Analyzer for Gate-level netlist & SPICE netlist |
| |
|
| |
|
 |
INCENTIA
Full-Chip Gate-level Static Timing Analyzer |
| |
|
 |
Legend Design
Best-in-class characterization tool for memory, standard cell and I/O cell.
High-Speed & High-accuracy Circuit Simulator |
| |
|
 |
Mentor Graphics
ModelSim, Questa, Calibre, ADvanceMS, ADiT, 0-in
Catapult-C, Precision, PADS, Board Station, Expedition HyperLynx, Veloce, etc.
|
| |
|
 |
Orora Design Technologies
Parasitic-included Optimization & Behavioral Model Generation from SPICE to Verilog/VHDL AMS/Matlab
|
| |
|
 |
Temento Systems
On-Chip FPGA verification Tool
|
| |
|
 |
TOOL CORPORATION
Next Generation fastest Layout Viewer & Fracturing solution |
| |
|
|
|
